A. Field of the Invention
This invention relates to the field of art of high speed dynamic flip-flops.
B. Prior Art
Timing devices are known in which a high frequency crystal controlled oscillator is followed by a series of dynamic flip-flops where the output pulse rate or frequency is a binary submultiple of the crystal frequency. Using integrated circuit technology, the oscillator and the dynamic flip-flops have been formed on a single chip. Since the cost of a crystal decreases as its operating frequency increases it has been desirable to use crystals of as high a frequency as possible. However, the finite slew rates and propagation times associated with the transistors of the first in the series of dynamic flip-flops imposes an upper limit on the crystal frequency at which consistent and reliable operation may be obtained.
It has previously been possible to reduce slew rates and propagation delays of transistors by increasing their area on the surface of the chip. However, this is undesirable since increasing the area of the transistor increases the size of the overall circuit and correspondingly, fewer circuits may be obtained from a given diameter wafer thereby increasing the cost of each circuit. Another penalty imposed by increasing the transistor area is the attendant increase in junction capacitance which causes a corresponding increase in charging current during each transition of the dynamic flip-flop. At high frequencies, this adds significantly to the total chip current drain from the power supply.
A further problem involving the yield of chips from a wafer results from the variations of transistor area from the nominal limits established by the masks and the variation in the diffusion depth during manufacture. In every wafer, a certain percentage of transistors have exhibited longer slew times and longer propagation times (lower gain) than required for a maximum specified crystal frequency and thus entire circuits must be discarded thereby lowering the yield. If the crystal frequency were the same but the gain requirements were decreased, then there would be a resultant increase in the yield.
Accordingly, an object of the present invention is matching the duty cycle of the input clock pulses to the ratio of propogation delays of the master and slave portions of a flip-flop to obtain a higher operating frequency with gates of given gain or to achieve acceptable operation with gates of lower gain at a given operating frequency.